Simplified Design & Automation

Overview of Services

Our designers are experts in the SoC design flow process from performing specialized tasks, and working on individual blocks, to full-chip implementations. If you are migrating your design to an advanced process node, we can assist you in achieving better results faster, avoiding common pitfalls.

Consulting

Whether you need to prove IP performance feasibility or migrate to a faster process node, we offer more than the standard consulting services. Allow us to setup the flow, create a floorplan and perform synthesis-through-route-optimization tasks, including static timing and extraction.

Design

At advanced nodes, reducing design time requires innovation across the infrastructure and toolchain due to high process complexity. We provide planning, implementation, and verification for either RTL or Netlist to GDS workflows.
  • Design Planning
  • Synthesis
  • Place and Route
  • EMIR, LVS, FV, PNR
  • Static Timing Analysis
  • Full Test Chip

Training

Floor Planning
Best practices and tools for optimizing system level PPA and turn around time. How to choose, enable and execute bottoms up, narrow channel, or full abutment designs.
Tool Training
How to get the most out of the industry leading PnR tools and integrate with analysis tools from various vendors as well as open source. Learn how to create a truly vendor agnostic environment for improved productivity and vastly reduced licensing fees.
TCL & Python Programming Language
Learn how to write efficient and reusable code that can automate nearly any task or extract any data you need from your designs.

Get there faster.


About Us
JDWK founder, Justin Kernen, is a 20-year veteran hardware engineer with expertise in RTL2GDS. He has taped out dozens of chips for Intel, Apple, and Microsoft. Our engineers have worked on chips ranging from 90nm to 3nm.