Simplified Design & Automation

Overview of Services

Our designers are experts in the SoC design flow process from performing specialized tasks, and working on individual blocks, to full-chip implementations. If you are migrating your design to an advanced process node, we can assist you in achieving better results faster, avoiding common pitfalls.

Consulting

Whether you need to prove IP performance feasibility or migrate to a faster process node, we offer more than the standard consulting services. Allow us to setup the flow, create a floorplan and perform synthesis-through-route-optimization tasks, including static timing and extraction.

Design

At advanced nodes, reducing design time requires technology innovation across the infrastructure and toolchain due to high process complexity. We provide planning, Implementation, Verification, RTL/Netlist to GDS
  • EMIR, LVS, FV, PNR
  • Static Timing Analysis
  • Synthesis
  • Full Test Chip

Training

Floor Planning
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Tool Training
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TCL & Python Programming Language
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About Us
JDWK founder, Justin Kernen, is a 20-year veteran hardware engineer with expertise in RTL2GDS. He has taped out dozens of chips for Intel, Apple, and Microsoft. Our engineers have worked on chips ranging from 90nm to 3nm.